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? semiconductor components industries, llc, 2014 january, 2014 ? rev. 5 1 publication order number: ncP6924/d ncP6924 6 channel pmic with 2 dcdc converters and 4 ldos the ncP6924 integrated circuit is part of the on semiconductor mini power management ic family (pmic). it is optimized to supply battery powered portable application sub ? systems such as camera function, microprocessors. this device integrates two high efficiency up to 1.0 a step ? down dcdc converters with dynamic voltage scale (dvs) and 4 low dropout (ldo) voltage regulators in a wlcsp30 2.46 x 2.06 mm package. features ? 2 dcdc converters (3 mhz, 1 h/10 f, up to 1.0 a) ? peak efficiency 95% ? programmable output voltage: 0.6 v to 3.3 v by 12.5 mv steps ? 4 low noise ? low drop out regulators (2.2 f, 150 ma and 300 ma) ? programmable output voltage: 1.0 v to 3.3 v by 50 mv steps ? 50 vrms typical low output noise ? control ? 400 khz / 3.4 mhz i 2 c compatible ? independent enable pins or i 2 c enable control bits ? power good and interrupt output pin ? customizable power up sequence ? extended input voltage range from 2.3 v to 5.5 v ? 105 a very low quiescent current at no load ? less than 1 a off mode current ? small footprint: 2.46 x 2.06 mm wlcsp 0.4 mm pitch ? these are pb ? free devices typical applications ? cellular phones, tablets ? digital cameras power state indicator processor interrupt processor i c battery or system supply processor or system supply dcdc1 out dcdc2 out 4.7 uf 1. 0uf i c ncP6924 interrupt supply monitoring core power up sequencer thermal protection avin agnd sda scl pg hwen intb endcdc1 endcdc2 enldo2 enldo2 enldo3 enldo4 system supply 4.7uf 10uf 1uh fb1 pvin1 sw1 pgnd1 dcdc1 up to 1.0a d6 e4 e6 c6 system supply 10uf 1uh fb2 pvin2 sw2 pgnd2 dcdc2 up tp 850ma b6 b4 a6 c5 system or dcdc supply system or dcdc supply ldo1 out ldo2 out 2.2uf 2.2uf ldo4 out 2.2uf ldo3 out 2.2uf system or dcdc supply ldo1 300ma ldo2 300ma ldo3 150ma ldo4 150ma vin1 vout1 vin2 vout2 vout3 vin4 vout4 rev 1. 00 a4 a3 e3 e2 c1 b1 a1 enabling c2 d3 d5 d2 d1 a5 b2 a2 e5 d4 b5 e1 b3 figure 1. application schematic wlcsp30 case 567cu marking diagram* http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 39 of this data sheet. ordering information xx = ah for ncP6924ah (hwen version) = ae for ncP6924ae (enable version) = bh for ncP6924bfcht1g = ch for ncP6924cfcht1g a = assembly location wl = wafer lot y = year ww = work week = pb ? free package (pb ? free indicator, ?g? or microdot ? ?, may or may not be present.) 6924xx awlyww a b c d e 123456 sw1 pg fb1 vout1 vin1 pgnd1 endcdc1 hwen agnd enldo3 pvin1 pvin2 nc nc avin pgnd2 endcdc2 fb enldo2 sda sw2 intb vout2 vin2 scl enldo1 enldo4 vout4 vin34 vout3 (top view) 30 pins 2.46 x 2.06 mm wlcsp, 0.44 mm pitch
ncP6924 http://onsemi.com 2 dc to dc 1 up to 1.0 a step ? down converter pvin1 sw1 fb1 pgnd1 ldo1 300 ma ldo ldo2 300 ma ldo vout1 vin1 ldo4 150 ma ldo vout4 agnd thermal shutdown serial interface scl sda control endcdc1 intb pg avin ldo3 150 ma ldo vout3 vin34 endcdc2 enldo1 enldo2 enldo3 hwen enldo4 dc to dc 2 up to 850 ma step ? down converter sw2 fb2 pgnd2 pvin2 vout2 vin2 uvlo vref osc figure 2. functional block diagram
ncP6924 http://onsemi.com 3 pin out description a b c d e 123456 sw1 pg fb1 vout1 vin1 pgnd1 endcdc1 hwen agnd enldo3 pvin1 pvin2 nc nc avin pgnd2 endcdc2 fb enldo2 sda sw2 intb vout2 vin2 scl enldo1 enldo4 vout4 vin34 vout3 figure 3. pin out (top view) table 1. pin function description pin name type description supply c2 avin analog input analog supply. this pin is the device analog and digital supply. a 1.0 f ceramic capacitor or larger must bypass this input to ground. this capacitor should be placed as close as possible to this pin. d3 agnd analog ground analog ground. analog and digital modules ground. must be connected to the system ground. control and serial interface d4 hwen digital input hardware enable. active high will enable the part. there is an internal pull down resistor on this pin. d5 endcdc1 digital input dcdc1 enable. active high will enable dcdc1. there is internal pull down resistor on this pin. b5 endcdc2 digital input dcdc2 enable, active high will enable dcdc2. there is internal pull down resistor on this pin. e1 enldo1 digital input ldo1 enable, active high will enable ldo1. there is internal pull down resistor on this pin. b3 enldo2 digital input ldo2 enable, active high will enable ldo2. there is internal pull down resistor on this pin. d2 enldo3 digital input ldo3 enable active high will enable ldo3. there is internal pull down resistor on this pin. d1 enldo4 digital input ldo4 enable active high will enable ldo4. there is internal pull down resistor on this pin. a2 scl digital input i 2 c interface clock line b2 sda digital input/output i 2 c interface bi ? directional data line. e5 pg digital output power good open drain output. a5 intb digital output interrupt open drain output. dcdc converters c6 pvin1 power input dcdc1 power supply. this pin must be decoupled to ground by a 4.7 f ceramic capacitor. this capacitor should be placed as close as possible to this pin. e6 sw1 power output dcdc1 switch power. this pin connects the power transistors to one end of the inductor. typical application uses 1.0 h inductor; refer to application section for more information. e4 fb1 analog input dcdc1 feedback voltage. this pin is the input to the error amplifier and must be connected to the output capacitor.
ncP6924 http://onsemi.com 4 table 1. pin function description pin description type name dcdc converters d6 pgnd1 power ground dcdc1 power ground. this pin is the power ground and carries the high switching current. a high quality ground must be provided to prevent noise spikes. a local ground plane is recommended to avoid high ? density current flow in a limited pcb track.. c5 pvin2 power input dcdc2 power supply. this pin must be decoupled to ground by a 4.7 f ceramic capacitor. this capacitor should be placed as close as possible to this pin. a6 sw2 power output dcdc2 switch power. this pin connects the power transistors to one end of the inductor. typical application uses 1.0 h inductor; refer to application section for more information. b4 fb2 analog input dcdc2 feedback voltage. this pin is the input to the error amplifier and must be connected to the output capacitor. b6 pgnd2 power ground dcdc1 power ground. this pin is the power ground and carries the high switching current. a high quality ground must be provided to prevent noise spikes. a local ground plane is recommended to avoid high ? density current flow in a limited pcb track. ldo regulators e2 vin1 power input ldo1 power supply. e3 vout1 power output ldo1 output power. this pin requires a 2.2 f decoupling capacitor. a3 vin2 power input ldo2 power supply a4 vout2 power output ldo2 output power. this pin requires a 2.2 f decoupling capacitor. b1 vin34 power input ldo3 & ldo4 power supply a1 vout3 power output ldo3 output power. this pin requires a 2.2 f decoupling capacitor. c1 vout4 power output ldo4 output power. this pin requires a 2.2 f decoupling capacitor. table 2. maximum ratings (note 1) rating symbol value unit analog and power pins: avin, pvin1, sw1, pvin2, sw2, vin1, vout1, vin2, vout2, vin34, vout3, vout4, pg, intb, fb1, fb2 v a ? 0.3 to + 6.0 v digital pins: scl, sda, hwen, endcdc1, endcdc2, enldo1, enldo2, en- ldo3, enldo4: input voltage input current v dg i dg ? 0.3 to v a +0.3 6.0 10 v ma human body model (hbm) esd rating (note 2) esd hbm 2000 v machine model (mm) esd rating (note 2) esd mm 200 v latch up current: (note 3) all digital pins all other pins i lu 10 100 ma storage temperature range t stg ? 65 to + 150 c maximum junction temperature t jmax ? 40 to +150 c moisture sensitivity (note 4) msl level 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. all voltages are related to agnd. 2. esd rated to the following: human body model (hbm) 2.0 kv per jedec standard: jesd22 ? a114. machine model (mm) 200 v per jedec standard: jesd22 ? a115. 3. latch up current per jedec standard: jesd78 class ii. 4. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020a.
ncP6924 http://onsemi.com 5 table 3. recommended operating conditions symbol parameter conditions min typ max unit av in, pv in analog and power supply 2.3 5.5 v ldo vin ldo input voltage range 1.7 5.5 v t a ambient temperature range ? 40 25 +85 c t j junction temperature range (note 6) ? 40 25 +125 c r ja thermal resistance junction to ambient (note 7) wlcsp30 on demo ? board ? 55 ? c/w p d power dissipation rating (note 8) t a 85 c ? 730 ? mw t a = 40 c ? 1550 ? mw l inductor for dc to dc converters (note 5) 0.5 1 2.2 h co output capacitor for dc to dc converters (note 5) 5 10 40 f output capacitors for ldo (note 5) 1.20 2.2 5.0 f c in input capacitor for dc to dc converters (note 5) 3.0 4.7 ? f 5. refer to the application information section of this data sheet for more details. 6. the thermal shutdown set to 150 c (typical) avoids potential irreversible damage on the device due to power dissipation. 7. the r ja is dependent of the pcb heat dissipation. board used to drive this data was a ncP6924evb board. it is a multilayer board with 1 ? once internal power and ground planes and 2 ? once copper traces on top and bottom of the board. 8. the maximum power dissipation (p d ) is dependent by input voltage, maximum output current and external components selected. r ja 125 t a p d table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. av in = pv in1 = pv in2 = v in1 = v in2 = v in34 = 3.6 v and default configuration, unless otherwise specified. typical values are referenced to t j = +25 c and default configuration, unless otherwise specified (note 11). symbol parameter conditions min typ max unit supply current: pins av in ? pv in1 ? pv in2 ? v in1 ? v in2 ? v in34 iq operating quiescent current dcdc1&2 on, no load, no switching ldos off, t a = up to +85 c ? 60 100 a dcdc1&2 on, no load, no switching ldos on, no load, t a = up to +85 c ? 105 190 dcdc1&2 off ldos on, no load, t a = up to +85 c ? 55 100 isleep sleep mode current hwen pin on all dc to dc and ldos off v in = 2.3 v to 5.5 v, t a = up to +85 c ? 7 15 a ioff shutdown current all dcdcs and ldos off hwen pin = off i 2 c interface disabled v in = 2.3 v to 5.5 v, t a = up to +85 c ? 0.1 2.0 a dcdc1&2 step down converters pv in1,2 input voltage range 2.3 ? 5.5 v i outmax maximum output current ncP6924afcht1g (dcdc1&2) & ncP6924afcet1g (dcdc1&2) 0.80 ? ? a ncP6924bfcht1g (dcdc1&2), ncP6924cfcht1g (dcdc2) 0.85 ? ? ncP6924cfcht1g (dcdc1) 1.00 ? ? v out output voltage dc error i out = 300 ma ? 1 0 1 % 9. enx (enable control signal of output channel, endcdc1, endcdc2, enldo1, enldo2, enldo3, enldo4). 10. devices that use non ? standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull ? up resistors r p are connected. 11. refer to the application information section of this data sheet for more details. 12. guaranteed by design and characterized.
ncP6924 http://onsemi.com 6 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. av in = pv in1 = pv in2 = v in1 = v in2 = v in34 = 3.6 v and default configuration, unless otherwise specified. typical values are referenced to t j = +25 c and default configuration, unless otherwise specified (note 11). symbol unit max typ min conditions parameter dcdc1&2 step down converters f sw switching frequency 2.7 ? 3.3 mhz r onhs p ? channel mosfet on resist- ance from pvin1 / pvin2 pins to sw1 / sw2 pins t j up to 85 c, pv in = 5.5 v ? 250 ? m r onls n ? channel mosfet on resist- ance from sw1 / sw2 pins to pgnd1 / pgnd2 pins, t j up to 85 c, pv in = 5.5 v ? 200 ? m i pk peak inductor current open loop, 2.3 v pv in1,2 5.5 v ncP6924afcht1g (dcdc1&2) & ncP6924afcet1g (dcdc1&2) 1.00 1.30 1.60 a open loop, 2.3 v pv in1,2 5.5 v ncP6924bfcht1g (dcdc1&2), ncP6924cfcht1g (dcdc2) 1.05 1.35 1.65 open loop, 2.3 v pv in1,2 5.5 v ncP6924cfcht1g (dcdc1) 1.20 1.60 2.00 load regulation i out from 300 ma to i outmax ? 5 ? mv/a line regulation i out = 300 ma 2.3 v pv in1 5.5 v ? 0 ? mv d maximum duty cycle ? 100 ? % t start soft ? start time time from i 2 c command ack to 90% of out- put voltage ? ? 1 ms r disdcdc dcdc active output discharge ? 7 ? ldo1 and ldo2 v in1,2 ldo1 and ldo2 input voltage range, 300 ma load v out 1.5 v, i out = 300 ma 1.7 ? 5.5 v v out > 1.5 v, i out = 300 ma v out + v drop ? 5.5 i outmax1,2 maximum output current 300 ? ? ma i sc1,2 short circuit protection 360 ? 700 ma v out1,2 output voltage accuracy dc i out = 300 ma ? 2 v nom +2 % load regulation i out = 0 ma to 300 ma ? 0.4 ? % line regulation v in = max(1.7 v, v out + v drop ) to 5.5 v i out = 300 ma ? 0.3 ? % v drop dropout voltage i out = 300 ma, v out = v nom ? 2% v out = 1.8 v ? 130 250 mv i out = 300 ma, v out = v nom ? 2% v out = 2.8 v ? 90 200 mv psrr ripple rejection f = 1 khz v out = 1.1 v, i out = 100 ma ? ? 65 ? db f = 10 khz v out = 1.1 v, i out = 100 ma ? ? 55 ? noise 100 hz 100 khz, v out = 1.1 v, i out = 100 ma ? 55 ? v r disldo1,2 ldo active output discharge ? 25 ? 9. enx (enable control signal of output channel, endcdc1, endcdc2, enldo1, enldo2, enldo3, enldo4). 10. devices that use non ? standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull ? up resistors r p are connected. 11. refer to the application information section of this data sheet for more details. 12. guaranteed by design and characterized.
ncP6924 http://onsemi.com 7 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. av in = pv in1 = pv in2 = v in1 = v in2 = v in34 = 3.6 v and default configuration, unless otherwise specified. typical values are referenced to t j = +25 c and default configuration, unless otherwise specified (note 11). symbol unit max typ min conditions parameter ldo3 and ldo4 v in34 ldo3 and ldo4 input voltage v out 1.5 v, i out = 150 ma 1.7 ? 5.5 v v out > 1.5 v, i out = 150 ma v out + v drop ? 5.5 i outmax3,4 maximum output current 150 ? ? ma i sc3,4 short circuit protection 200 ? 600 ma v out output voltage accuracy i out = 150 ma ? 2 v nom +2 % load regulation i out = 0 ma to 150 ma ? 0.4 ? % line regulation v in = max(1.7 v, v out + v drop ) to 5.5 v i out = 150 ma ? 0.3 ? % v drop dropout voltage i out = 150 ma, v out = v nom ? 2% v out = 1.8 v ? 110 230 mv i out = 150 ma, v out = v nom ? 2 % v out = 2.8 v 70 180 psrr ripple rejection f = 1 khz v out = 1.1 v, i out = 100 ma ? ? 65 ? db f = 10 khz v out = 1.1 v, i out = 100 ma ? ? 55 ? noise 10 hz 100 khz v out = 1.1 v, i out = 100 ma 55 v r disldo3,4 ldo active output discharge ? 25 ? hwen / enx (note 9) v ih positive going input high voltage threshold 1.1 ? ? v v il negative going input low voltage threshold ? ? 0.4 v t fr enable pin filter (note 12) 4 ? 9 s i pd enable pins pull ? down (input bias current) ? 0.1 1.0 a pg v pgl power good low threshold falling edge as a percentage of nominal out- put voltage 86 90 of v nom 94 % v pghys power good detection level 0 3 5 % t rt power good reaction time dcdc case falling (note 12) rising (note 12) ? 4 5 ? ? 9 s power good reaction time ldo case falling (note 12) rising (note 12) ? 228 5 ? ? 265 s v pgl power good low output voltage i pg = 5 ma ? ? 0.2 v pg lk power good leakage current 3.6 v at pg pin when power good valid ? ? 100 na v pgh power good high output voltage open drain ? ? 5.5 v 9. enx (enable control signal of output channel, endcdc1, endcdc2, enldo1, enldo2, enldo3, enldo4). 10. devices that use non ? standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull ? up resistors r p are connected. 11. refer to the application information section of this data sheet for more details. 12. guaranteed by design and characterized.
ncP6924 http://onsemi.com 8 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. av in = pv in1 = pv in2 = v in1 = v in2 = v in34 = 3.6 v and default configuration, unless otherwise specified. typical values are referenced to t j = +25 c and default configuration, unless otherwise specified (note 11). symbol unit max typ min conditions parameter intb v intbl intb low output voltage i intb = 5 ma 0 ? 0.2 v v intbh intb high output voltage open drain ? ? 5.5 v intb lk intb leakage current 3.6 v at intb pin when intb valid ? ? 100 na i 2 c v i2cint high level at scl/sda line ? ? 5.0 v v i2cil scl, sda low input voltage scl, sda pin (notes 10 and 12) ? ? 0.5 v v i2cih scl, sda high input voltage scl, sda pin (notes 10 and 12) 0.8xv i2c int ? ? v v i2col scl, sda low output voltage i sink = 3 ma (note12) ? ? 0.4 v f scl i 2 c clock frequency (note 12) ? ? 3.4 mhz total device v uvlo under voltage lockout v in falling ? ? 2.3 v v uvloh under voltage lockout hysteresis v in rising 60 ? 200 mv t sd thermal shut down protection ? 150 ? c t warning warning rising edge ? 135 ? c t sdhys thermal shut down hysteresis ? 35 ? c 9. enx (enable control signal of output channel, endcdc1, endcdc2, enldo1, enldo2, enldo3, enldo4). 10. devices that use non ? standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull ? up resistors r p are connected. 11. refer to the application information section of this data sheet for more details. 12. guaranteed by design and characterized.
ncP6924 http://onsemi.com 9 typical operating characteristics av in = pv in1 = pv in2 = v in1 = v in2 = v in34 = 3.6 v (unless otherwise noted). t j = +25 c, dcdc1 = 1.25 v, dcdc2 = 1.85 v, ldo1&3 = 2.80 v, ldo3&4 = 1.80 v, c ldo = 2.2 f 0603, l dcdc = 1.0 f (lqh44pn1r0np02) ? c dcdc = 10 f 0603 figure 4. dcdc1 efficiency vs. iout (auto mode) vout = 3.3 v figure 5. dcdc1 efficiency vs. i out (auto mode) v out = 0.6 v figure 6. dcdc1 efficiency vs. i out (auto mode) v out = 1.25 v figure 7. dcdc1 efficiency vs. i out (auto mode) v out = 1.85 v
ncP6924 http://onsemi.com 10 typical operating characteristics av in = pv in1 = pv in2 = v in1 = v in2 = v in34 = 3.6 v (unless otherwise noted). t j = +25 c, dcdc1 = 1.25 v, dcdc2 = 1.85 v, ldo1&3 = 2.80 v, ldo3&4 = 1.80 v, c ldo = 2.2 f 0603, l dcdc = 1.0 f (lqh44pn1r0np02) ? c dcdc = 10 f 0603 figure 8. dcdc2 efficiency vs. i out (auto mode) v out = 0.6 v figure 9. dcdc2 efficiency vs. i out (auto mode) v out = 1.25 v figure 10. dcdc2 efficiency vs. i out (auto mode) v out = 1.85 v figure 11. dcdc2 efficiency vs. i out (auto mode) v out = 3.3 v
ncP6924 http://onsemi.com 11 typical operating characteristics av in = pv in1 = pv in2 = v in1 = v in2 = v in34 = 3.6 v (unless otherwise noted). t j = +25 c, dcdc1 = 1.25 v, dcdc2 = 1.85 v, ldo1&3 = 2.80 v, ldo3&4 = 1.80 v, c ldo = 2.2 f 0603, l dcdc = 1.0 f (lqh44pn1r0np02) ? c dcdc = 10 f 0603 figure 12. dcdc1 ripple voltage in pwm mode (v in = 3.6 v ? v out = 1.25 v ? i out = 100 ma) figure 13. dcdc2 ripple voltage in pwm mode (v in = 3.6 v ? v out = 1.85 v ? i out = 175 ma) figure 14. dcdc1 ripple voltage in pfm mode (v in = 3.6 v ? v out = 1.25 v ? no load) figure 15. dcdc2 ripple voltage in pfm mode (v in = 3.6 v ? v out = 1.85 v ? no load)
ncP6924 http://onsemi.com 12 typical operating characteristics av in = pv in1 = pv in2 = v in1 = v in2 = v in34 = 3.6 v (unless otherwise noted). t j = +25 c, dcdc1 = 1.25 v, dcdc2 = 1.85 v, ldo1&3 = 2.80 v, ldo3&4 = 1.80 v, c ldo = 2.2 f 0603, l dcdc = 1.0 f (lqh44pn1r0np02) ? c dcdc = 10 f 0603 figure 16. dcdc1 load transient response (pwm mode, v in = 3.6 v ? v out = 1.25 v) figure 17. dcdc2 load transient response (pwm mode, v in = 3.6 v ? v out = 1.85 v) figure 18. ldo1 load transient response (v in = 3.6 v ? v out = 2.80 v) figure 19. ldo4 load transient response (v in = 3.6 v ? v out = 1.80 v)
ncP6924 http://onsemi.com 13 typical operating characteristics av in = pv in1 = pv in2 = v in1 = v in2 = v in34 = 3.6 v (unless otherwise noted). t j = +25 c, dcdc1 = 1.25 v, dcdc2 = 1.85 v, ldo1&3 = 2.80 v, ldo3&4 = 1.80 v, c ldo = 2.2 f 0603, l dcdc = 1.0 f (lqh44pn1r0np02) ? c dcdc = 10 f 0603 figure 20. dcdc soft ? start (inrush current, v in = 3.6 v ? v out = 1.25 v) figure 21. i 2 c shutdown sequence with active discharge enabled figure 22. hwen shutdown sequence with active discharge disabled
ncP6924 http://onsemi.com 14 typical operating characteristics av in = pv in1 = pv in2 = v in1 = v in2 = v in34 = 3.6 v (unless otherwise noted). t j = +25 c, dcdc1 = 1.25 v, dcdc2 = 1.85 v, ldo1&3 = 2.80 v, ldo3&4 = 1.80 v, c ldo = 2.2 f 0603, l dcdc = 1.0 f (lqh44pn1r0np02) ? c dcdc = 10 f 0603 figure 23. ldo1 psrr (v in = 3.6 v ? v out = 1.1 v ? i out = 100 ma) figure 24. ldo1 output noise (v in = 3.6 v ? v out = 1.1 v ? i out = 100 ma) figure 25. ldo4 psrr (v in = 3.6 v ? v out = 1.1 v ? i out = 100 ma) figure 26. ldo4 output noise (v in = 3.6 v ? v out = 1.1 v ? i out = 100 ma)
ncP6924 http://onsemi.com 15 detailed operating description general description the ncP6924 mini power management integrated circuit is optimized to supply different sub systems of battery powered portable applications. the ic can be supplied directly from the latest technology single cell batteries such as lithium ? polymer as well as from triple alkaline cells. alternatively, the ic can be supplied from a pre ? regulated supply rail in case of multi ? cell or main powered applications. it integrates two switched mode dcdc converters and four low dropout linear regulators. the ic is widely programmable through an i 2 c interface and includes low level io signaling. an analog core provides the necessary references for the ic while a digital core ensures proper control. the output voltage range, current capabilities and performance of the switched mode dcdc converters are well suited to supply the different peripherals in the system as well as to supply processor cores. to reduce overall power consumption of the application, dynamic voltage scaling (dvs) is supported on the dcdc converters. for pwm operation, the converters run on a local 3mhz clock. a low power pfm mode is provided that ensures that even at low loads high efficiency can be obtained. all the switching components are integrated including the compensation networks and synchronous rectifier. only a small sized 1uh inductor and 10 f bypass capacitor are required for typical applications. the general purpose low dropout regulators can be used to supply the lower power rails in the application. to improve the overall application standby current, the bias current of these regulators are made very low. the regulators have their own input supply pin to be able to connect them independently to either the system supply voltage or to the output of the dcdc converter in the application. the regulators are bypassed with a small size 2.2uf capacitor. the feature can be controlled through the i 2 c interface. in addition to this bus, digital control pins including hardware enable (hwen), individual enable (enx), power good (pg) and interrupt (intb) are provided. two different enable versions are available: ? the 6924xh version offers one master enable pin (hwen) with default power up sequence factory programmed (customizable upon request) and modifiable via i 2 c. ? the 6924xe version ignores the hwen pin. in this case pulling high one of the enable pins endcdcx or enldox will enable the corresponding supply without initiating a power up sequence (this version does not require i 2 c). under voltage lockout the core does not operate for voltages below the under voltage lock out (uvlo) level. below the uvlo threshold, all internal circuitry (both analog and digital) is held in reset. ncP6924 operation is guaranteed down to uvlo when battery voltage is dropping off. to avoid erratic on / off behaviour, a maximum 200 mv hysteresis is implemented. restart is guaranteed at 2.5 v when vbat voltage is recovering or rising. thermal shutdown the thermal capabilities of the device can be exceeded due to the output power capabilities of the on chip step down converters and low d rop out regulators. a thermal protection circuit is therefore implemented to prevent the part from being damaged. this protection circuit is only activated when the core is in active mode (at least one output channel is enabled). during thermal shutdown, all outputs of the ncP6924 are off. when the ncP6924 returns from thermal shutdown mode, it can re ? start in three different configurations depending on rearm[1:0] bits: ? if rearm[1:0] = 00, ncP6924 re ? starts with default register values, ? if rearm[1:0] = 01 ncP6924 re ? starts with register values set prior to thermal shutdown, ? finally if rearm[1:0] = 10, ncP6924 does not re ? start automatically, a toggle of hwen or enx pins is needed. in addition, a thermal warning is implemented which can inform the processor through an interrupt (if not masked) that ncP6924 is close to its thermal shutdown so that preventive measurement can be taken by software. active output discharge active output discharge can be independently enabled / disabled by the app ropriate settings in the dis register (refer to the register definition section). however to prevent any disturbances on the power ? up sequence, a quick active output discharge is done during the start ? up sequence for all output channels. when the ic is turned off through hwen pin (or enx pins) or avin drops down below uvlo threshold, no shut down sequence is expected, all supplies are disabled and outputs discharged simultaneously if discharge enabled.
ncP6924 http://onsemi.com 16 enabling 6924xh case (hwen version) the hwen pin controls the device start up. if hwen is raised, this starts the power up sequencer. if hwen is made low, device enters in shutdown mode and all regulators are turned off. a built ? in pull ? down resistor disables the device if this pin is left unconnected. when hwen is high, the different power rails can be independently enabled / disabled by writing the appropriate bit in the enable register or by changing enable pins (enx) state (see table 7). power up sequence and hwen when enabling the part with the hwen pin, the part will start up in the configuration factory programmed in the registers. any order and output voltage setting can be factory programmed upon request. by default, the power up sequence is the following: table 5. default power up sequence for ncP6924ah delay (in ms) default assignment default v prog default mode and on/off 2 dcdc1 1.25 v auto mode on 4 dcdc2 1.85 v auto mode on 6 ldo1 2.8 v on 8 ldo2 1.8 v on 10 ldo3 2.8 v on 12 ldo4 1.8 v on table 6. default power up sequence for ncP6924bh and ncP6924ch delay (in ms) default assignment default v prog default mode and on/off 2 dcdc1 1.2 v forced pwm off 4 dcdc2 1.8 v auto mode off 6 ldo1 2.9 v off 8 ldo2 2.85 v off 10 ldo3 1.8 v off 10 ldo4 1.8 v off i 2 c registers can be read and written while hwen pin is still low. by programming the appropriate registers (see registers description section), the power up sequence can be modified. reset to the factory default configuration can be achieved either by hardware reset (all power supplies removed) or by writing through the i 2 c in the reset register. enable control table 7. truth table of enable/disable control 6924xh hwen pin endcdcx enldox pins endcdcx enldox registers bits outputx enabled / disabled h l 0 disabled h l 1 enabled h h 0 enabled h h 1 enabled l * * disabled note: * means undefined shutdown when shutting down the device, no shut down sequence is applied. all supplies are disabled and outputs are discharged simultaneously, and pg open drain output is low whereas intb open drain is released. however, the power down sequence can be achieved by disabling dcdc/ldos via i 2 c and/or enx pins before setting hwen pin to low.
ncP6924 http://onsemi.com 17 t0 vout1 2.8v vout4 1.8v vout2 1.8v vout3 2.8v dcdc1 1.25v sequencer (2ms)* 36 ms (18 x tsequencer) t1 t2 t3 t4 t5 t6 t7 reset init time 160 us dvs ramp time hwen t17 init time 50 us init time 50 us init time 50 us init time 50 us t start bias ime 600 us dcdc2 1.85v init time 160 us dvs ramp time figure 27. default power up sequence 6924ah
ncP6924 http://onsemi.com 18 enabling 6924xe case (enable version) the hwen pin does not have any influence on the device, i 2 c ?enable? and ?tap? either. device starts up as soon as one enx rises. when the remaining enx pin is made low, device enters in shutdown mode. a built ? in pull ? down resistor disables the device if enx pins are left unconnected. the different power rails can be independently enabled / disabled by using the corresponding enx pin (see table 5). power up sequence the power up sequence is managed by the processor with the enx. the part will start up in the configuration factory programmed in the registers. any output voltage setting can be factory programmed upon request. by default, the power up is the following: table 8. default power up sequence 6924ae default assignment default vprog default mode dcdc1 1.25 v auto mode dcdc2 1.85 v auto mode ldo1 2.80 v ? ldo2 1.80 v ? ldo3 2.80 v ? ldo4 1.80 v ? i 2 c registers can be read and written while enx pins are low. by programming the appropriate registers (see registers description section), the power up can be modified. reset to the factory default configuration can be achieved either by hardware reset (all power supplies removed) or by writing through the i 2 c in the reset register. enable control table 9. truth table of enable/disable control 6924xe hwen pin endcdcx enldox pins endcdcx enldox registers bits outputx enabled / disabled * l * disabled * h * enabled *means undefined shutdown when shutting down the device, no shut down sequence is applied. all supplies are disabled and outputs are discharged simultaneously , and open drain outputs (pg and intb) are low. however, the power down sequence can be achieved by disabling dcdc/ldos via enx pins. figure 28. default power up sequence 6924ae vout1 2.8v vout4 1.8v dcdc1 1.25v 1.15ms reset init time 160 us endcdc1 enldo1 init time 50 us bias time 600 us dcdc2 1.85v dvs ramp time endcdc2 enldo4 inittime 160 us inittime 50 us dvs ramp time vout3 2.8v enldo2 enldo3 inittime 50 us vout2 1.8v inittime 50 us
ncP6924 http://onsemi.com 19 dynamic voltage scaling (dvs) the step down converters support dynamic voltage scaling (dvs). this means that the output voltage can be reprogrammed based upon the i 2 c commands to provide the different voltages required by the processor. the change between set points is managed in a smooth manner without disturbing the operation of the processor. when programming a higher voltage, the reference of the switcher and therefore the output is raised in equidistant steps per defined time period such that the dv/dt is controlled (by default 12.5 mv/1.33 s). when programming a lower voltage the output voltage will decrease accordingly. the dvs step is fixed and the speed is programmable. v2 v1 internal reference output voltage t v figure 29. default dynamic voltage scaling effect timing diagram programmability dcdc converter output voltage can be controlled by gox bit (time register) with vprogdcdcx[7:0] and vdvsdcdcx[7:0] registers. available output levels are listed in table vprogdcdcx[7:0] and vdvsdcdcx[7:0] in register description. gox bit determines whether dcdc output voltage value is set in vprogdcdcx[7:0] register or in vdvsdcdcx[7:0] register. table 10. go bit description gox bit description 0 output voltage is set to vprogdcdcx 1 output voltage is set to vdvsdcdcx the two dvs bits in the time register determine the ramp up time per each voltage step. table 11. dvs bits description dvs [1:0] bit description 00 1.33 s per step (default) 01 2.67 s per step 10 5.33 s per step 11 10.67 s per step there are two ways of i 2 c registers programming to switch the dcdc converters output voltages between different levels: ? preset vprogdcdcx[7:0] and vdvsdcdcx[7:0] registers, and start dvs sequence by changing gox bit state. ? gox bit remains unchanged, change output voltage value in either vprogdcdcx[7:0] or vdvsdcdcx[7:0] register. for example, the device needs to supply either 1.2 v or 0.9 v depending on working conditions. if using method 1, vprogdcdcx[7:0] and vdvsdcdcx[7:0] should be set as shown in table 8. gox bit should be programmed to 1 to change dcdcx output voltage from 1.2 v to 0.9 v, and be programmed to 0 to move back from 0.9 v to 1.2 v. table 12. vprogdcdc / vdvsdcdc settings for vdcdc switching between 1.2 v and 0.9 v register name values target vdcdc (v) vprogdcdc 0$30 1.2 vdvsdcdc 0$18 0.9 dcdc step down converter and ldo?s power good to indicate that the output of an output channel is established, a power good signal is available for each output channel. the power good signal is high when the channel is off and goes low when enabling the channel. once the output voltage reaches the expected output level, the power good signal becomes high again. when during operation the output gets below 90% of the expected level, the power good signal goes low which indicates a power failure. when the voltage rises again above 95% the power good signal goes high again. dcdc_en 160 us dcdc 95% 90% 4 ? 9 us 4 ? 9 us 5 us pg ldox_en ldox 95% 90% 228 ? 265 us 5 us pg 228 ? 265 us figure 30. dcdc channel internal power good signal figure 31. ldox channel internal power good signal
ncP6924 http://onsemi.com 20 power good assignment each channel generates an internal power good signal (either dcdc?s or ldo?s). these internal power good signals can be individually assigned to the pg pin through the pgood1 and pgood2 registers. the pg pin state is an and combination of assigned internal power good signals. by default only the power good signal of the dcdc?s converter is assigned. the pg pin is an open drain output. in addition, two other signals can be assigned to the pg pin: the internal reset signal through the pgood1 register and the dvs signal through the pgood2 register. by assigning the internal reset signal, the pg pin is held low throughout the power up sequence and the reset period. by assigning the dvs signal of the dcdc?s converter, the pg pin is made low during the period the output voltage is being raised to the new setting as shown in figure 32. i2c dcdcx pg initial value final value dvs start 95% of final value figure 32. pg operation in dvs sequence power good delay a delay can be programmed between the moment the and result of the assigned internal power good signals becomes high and the moment the pg pin is released. the delay is set from 0 ms to 512 ms through the tor[2:0] bits in the time register. internal signal(result of the assigned internal pg pg delay programmed in tor [2 :0] no delay figure 33. pg delay interrupt the interrupt controller continuously monitors internal interrupt sources, generating an interrupt signal when a system status change is detected (dual edge monitoring). the interrupt sources include: table 13. interrupt sources interrupt sources description pg_dcdc1 dcdc1 converter power good pg_dcdc2 dcdc2 converter power good pg_ldo1 ldo1 power good pg_ldo2 ldo2 power good pg_ldo3 ldo3 power good pg_ldo4 ldo4 power good uvlo uvlo state ildo1 ldo1 output over current ildo2 ldo2 output over current ildo3 ldo3 output over current ildo4 ldo4 output over current wnrg thermal warning tsd thermal shutdown individual bits generating interrupts will be set to 1 in the int_ack1/int_ack2 registers (i 2 c read only registers), indicating the interrupt source. int_ack1/int_ack2 registers are automatically reset by an i 2 c read. int_sen1/int_sen2 registers (read only registers) contain real time indicators of interrupt sources. all interrupt sources can be masked by writing registers int_msk1/int_msk2. masked sources will never generate an interrupt request on intb pin. the intb pin is an open drain output. a non masked interrupt request will result in the intb pin being driven low. when the host reads the int_ack1/int_ack2 registers the intb pin is released to high impedance and the interrupt registers int_ack1/int_ack2 are cleared. below figure shows how dcdc1 converter power good produces interrupt on intb pin with int_sen1/int_msk1/int_ack1 and an i 2 c read access (assuming no other interrupt happens during this read period). int_ack1[0] int_msk1[0] int_sen1[0] intb pin read read read read pg_dcdc1 figure 34. interrupt timing chart example of pg_dcdc1 i 2 c access on int_ack1 int_msk1 and int_msk2 registers are set to disable intb feature by default during power ? up.
ncP6924 http://onsemi.com 21 force reset and i 2 c interface disable the i 2 c interface can be disabled by the i2c_disable bit in the sync register. this saves current consumption which is especially of interest when all supply channels of the ncP6924 are disabled. to re ? activate the i 2 c, the ic needs to be enabled through the hwen pin. the i 2 c registers can be reset by setting the forcerst bit in register reset. it forces a restart of the device with its default settings. after startup the rststatus bit defaults to 1 and can be cleared through i 2 c. dcdc step down converters the dcdc converters are synchronous rectifier type with both high side and low side integrated switches. neither external transistor nor diodes are required for proper operation. feedback and compensation network are also fully integrated. the dcdc converters can operate in two dif ferent modes: pwm and pfm. the transition between pwm/pfm modes can occur automatically or the switcher can be placed in forced pwm mode by i 2 c programming. (modedcdc1 and modedcdc2 bits of enable register) pwm (pulse width modulation) operating mode in medium and high load conditions, dcdc converters operates in pwm mode from a fixed 3 mhz clock and adapts its duty cycle to regulate the desired output voltage. in this mode, the inductor current is in ccm (continuous current mode) and the voltage is regulated by pwm. the internal n ? mos switch operates as synchronous rectifier and is driven complementary to the p ? mos switch. in ccm the lower (n ? mos switch) in a synchronous converter provides a lower voltage drop than the diode in an asynchronous converter, which provides less loss and higher efficiency. pfm (pulse frequency modulation) operating mode in order to save power and improve ef ficiency at low loads the dcdc converters operate in pfm mode as the inductor drops into dcm (discontinuous current mode). the upper fet on time is kept constant and the switching frequency is variable. output voltage is regulated by varying the switching frequency which becomes proportional to loading current. as it does in pwm mode, the internal n ? mosfet operates as synchronous rectifier after each p ? mosfet on ? pulse with very small negative current limit. when load increases and current in inductor becomes continuous again, the controller automatically turns back to pwm fixed frequency mode. forced pwm the dcdc converters can be programmed to only use pwm and disable the transition to pfm if so desired. table 14. modedcdc1&2 bit description modedcdc1&2 bit description 0 auto switching pfm / pwm 1 forced pwm inductor peak current limitation during normal operation, peak current limitation will monitor and limit the current through the inductor. this current limitation is particularly useful when size and/or height constrains inductor power soft start a soft start is provided to limit inrush currents when enabling the converter. after enabling and internal delays elapsed, the dc to dc converter output will gradually ramp up to the programmed voltage. i 2 c compatible interface ncP6924 can support a subset of i 2 c protocol, below are detailed introduction for i 2 c programming.
ncP6924 http://onsemi.com 22 i 2 c communication description on semiconductor communication protocol is a subset of i 2 c protocol. start ic adress 1 1 read ack data 1 ack data n /ack stop start ack ic adress 0 0 write data1 ack data n ack /ack stop from mcu to ncpxxxx from ncpxxxx to mcu read out from part write inside part if part does not acknowledge, the /nack will be followed by a stop or sr. if part acknowledges, the ack can be followed by another data or stop or sr. figure 35. general protocol description the first byte transmitted is the chip address (with lsb bit sets to 1 for a read operation, or sets to 0 for a write operation). then the following data will be: ? in case of a write operation, the register address (@reg) we want to write in followed by the data we will write in the chip. the writing process is incremental. so the first data will be written in @reg, the second one in @reg + 1 .... the data are optional. ? in case of read operation, the ncP6924 will output the data out from the last register that has been accessed by the last write operation. like writing process, reading process is an incremental process. read out from part the master will first make a ?pseudo write? transaction with no data to set the internal address register. then, a stop then start or a repeated start will initiate the read transaction from the register address the initial write transaction has set: stop ic adress 1 1 read ack start ic adress 0 0 write register adress ack start ack data 1 data n ack /ack stop stets internal register pointer register adress value register adress + (n ? 1) value n registers read from mcu to ncpxxxx from ncpxxxx to mcu figure 36. read out from part the first write sequence will set the internal pointer on the register we want access to. then the read transaction will start at the address the write transaction has initiated.
ncP6924 http://onsemi.com 23 transaction with real write then read: with stop then start reg + (n ? 1) value ack stop from mcu to ncpxxxx from ncpxxxx to mcu start ic adress 0 0 write ack register reg0 address ack reg value ack sets internal register pointer write value in register reg0 write value in register reg0 + (n ? 1) n registers write ic adress 1 1 read start ack data 1 data k ack /ack stop regiister reg + (n ? 1) value register adress + (n ? 1) + (k ? 1) value k registers read figure 37. write followed by read transaction write in part: write operation will be achieved by only one transaction. after chip address, the mcu first data will be the internal register we want access to, then following data will be the data we want to write in reg, reg + 1, reg + 2, ...., reg +n. write n registers: reg+ ( n ? 1) value ack stop from mcu to ncpxxxx from ncpxxxx to mcu start ic adress 0 0 write ack register reg0 address ack reg value ack sets internal register pointer write value in register reg0 write value in register reg0 + (n ? 1) n registers write figure 38. write in n registers i 2 c address ncP6924 has fixed i 2 c but different i 2 c address (0$10, 7 bit address, see below table a7~a1), ncP6924 supports 7 ? bit address only. table 15. ncP6924 i 2 c address i 2 c address hex a7 a6 a5 a4 a3 a2 a1 a0 default, others $20 / $21 0 0 1 0 0 0 0 x other addresses are available upon request.
ncP6924 http://onsemi.com 24 register map following register map describes i 2 c registers. registers can be: r read only register rc read then clear rw read and write register rwm read, write and can be modified by the ic reserved address is reserved and register is not physically designed spare address is reserved and register is physically designed address register name type default function $00 int_ack1 rc $00 interrupt 1 register (dual edge) $01 int_ack2 rc $00 interrupt 2 register (rising edge and dual edge) $02 int_sen1 r $00 sense 1 register (real time status) $03 int_sen2 r $00 sense 2 register (real time status) $04 int_msk1 rw $ff mask 1 register to enable or disable interrupt sources $05 int_msk2 rw $ff mask 2 register to enable or disable interrupt sources $06 to $0f ? ? ? reserved for future use $10 reset rw $10 reset internal registers to default $11 pid r metal product identification (metal) $12 rid r metal revision identification (metal) $13 fid r fuse features identification (fuse) $14 enable rwm fuse ($fa) enable register (fuse) $15 dis rw fuse ($3f) active output discharge register (fuse) $16 pgood1 rw $43 power good pin assignment 1 $17 pgood2 rw $00 power good pin assignment 2 $18 time rw $00 timing definition $19 bucktap rw fuse ($08) buck sequencer register (fuse) $1a ldotap1 rw fuse ($1a) ldo1 and ldo2 sequencer register (fuse) $1b ldotap2 rw fuse ($2c) ldo3 and ldo4 sequencer register (fuse) $1c to $1f ? ? ? reserved for future use $20 vprogdcdc1 rw fuse ($34) dcdc1 output voltage setting $21 vprogdvs1 rw fuse ($34) dcdc1 dvs output voltage setting $22 vprogdcdc2 rw fuse ($64) dcdc2 output voltage setting $23 vprogdvs2 rw fuse ($64) dcdc2 dvs output voltage setting $24 vprogldo1 rw fuse ($24) ldo1 output voltage setting $25 vprogldo2 rw fuse ($10) ldo2 output voltage setting $26 vprogldo3 rw fuse ($24) ldo3 output voltage setting $27 vprogldo4 rw fuse ($10) ldo4 output voltage setting $28 to $3f ? ? ? reserved for future use
ncP6924 http://onsemi.com 25 registers description table 16. int_ack1 register name: int_ack1 address: $00 type: rc default: $00 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 ack_uvlo ack_pg_ldo4 ack_pg_ldo3 ack_pg_ldo2 ack_pg_ldo1 ack_pg_dcdc2 ack_pg_dcdc1 table 17. bit description of int_ack1 register bit bit description ack_pg_dcdc1 dcdc1 power good sense acknowledgement 0: cleared 1: dcdc1 power good event detected ack_pg_dcdc2 dcdc2 power good sense acknowledgement 0: cleared 1: dcdc2 power good event detected ack_pg_ldo1 ldo1 power good sense acknowledgement 0: cleared 1: ldo1 power good event detected ack_pg_ldo2 ldo2 power good sense acknowledgement 0: cleared 1: ldo2 power good event detected ack_pg_ldo3 ldo3 power good sense acknowledgement 0: cleared 1: ldo3 power good event detected ack_pg_ldo4 ldo4 power good sense acknowledgement 0: cleared 1: ldo4 power good event detected ack_uvlo under voltage sense acknowledgement 0: cleared 1: under voltage event detected table 18. int_ack2 register name: int_ack2 address: $01 type: rc default: $00 d7 d6 d5 d4 d3 d2 d1 d0 ack_tsd ack_wnrg ack_ildo4 ack_ildo3 ack_ildo2 ack_ildo1 spare = 0 spare = 0
ncP6924 http://onsemi.com 26 table 19. bit description of int_ack2 register bit bit description ack_ildo1 ldo1 over current sense acknowledgement 0: cleared 1: ldo1 over current event detected ack_ildo2 ldo2 over current sense acknowledgement 0: cleared 1: ldo2 over current event detected ack_ildo3 ldo3 over current sense acknowledgement 0: cleared 1: ldo3 over current event detected ack_ildo4 ldo4 over current sense acknowledgement 0: cleared 1: ldo4 over current event detected ack_wnrg thermal warning sense acknowledgement 0: cleared 1: thermal warning event detected ack_tsd thermal shutdown sense acknowledgement 0: cleared 1: thermal shutdown event detected table 20. int_sen1 register name: int_sen1 address: $02 type: r default: $00 d7 d6 d5 d4 d3 d2 d1 d0 spare=0 sen_uvlo sen_pg_ldo4 sen_pg_ldo3 sen_pg_ldo2 sen_pg_ldo1 sen_pg_dcdc2 sen_pg_dcdc1 table 21. bit description of int_sen1 register bit bit description sen_pg_dcdc1 dcdc1 power good sense 0: dcdc1 output voltage below target 1: dcdc1 output voltage within nominal range sen_pg_dcdc2 dcdc2 power good sense 0: dcdc2 output voltage below target 1: dcdc2 output voltage within nominal range sen _pg_ldo1 ldo1 power good sense 0: ldo1 output voltage below target 1: ldo1 output voltage within nominal range sen _pg_ldo2 ldo2 power good sense 0: ldo2 output voltage below target 1: ldo2 output voltage within nominal range sen _pg_ldo3 ldo3 power good sense 0: ldo3 output voltage below target 1: ldo3 output voltage within nominal range sen _pg_ldo4 ldo4 power good sense 0: ldo4 output voltage below target 1: ldo4 output voltage within nominal range sen _uvlo under voltage sense 0: input voltage higher than uvlo threshold 1: input voltage lower than uvlo threshold
ncP6924 http://onsemi.com 27 table 22. int_sen2 register name: int_sen2 address: $03 type: r default: $00 d7 d6 d5 d4 d3 d2 d1 d0 sen_tsd sen_wnrg sen_ildo4 sen_ildo3 sen_ildo2 sen_ildo1 spare = 0 spare = 0 table 23. bit description of int_sen2 register bit bit description 1: dcdc2 output current over limit sen _ildo1 ldo1 over current sense 0: ldo1 output current below limit 1: ldo1 output current over limit sen _ildo2 ldo2 over current sense 0: ldo2 output current below limit 1: ldo2 output current over limit sen _ildo3 ldo3 over current sense 0: ldo3 output current below limit 1: ldo3 output current over limit sen _ildo4 ldo4 over current sense 0: ldo4 output current below limit 1: ldo4 output current over limit sen _wnrg thermal warning sense 0: junction temperature below thermal warning limit 1: junction temperature over thermal warning limit sen _tsd thermal shutdown sense 0: junction temperature below thermal shutdown limit 1: junction temperature over thermal shutdown limit table 24. int_msk1 register name: int_msk1 address: $04 type: rw default: $ff d7 d6 d5 d4 d3 d2 d1 d0 spare=0 msk_uvlo msk_pg_ldo4 msk_pg_ldo3 msk_pg_ldo2 msk_pg_ldo1 msk_pg_dcdc2 msk_pg_dcdc1 table 25. bit description of int_msk1 register bit bit description msk _pg_dcdc1 dcdc1 power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk _pg_dcdc2 dcdc2 power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk _pg_ldo1 ldo1 power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk _pg_ldo2 ldo2 power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk _pg_ldo3 ldo3 power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked
ncP6924 http://onsemi.com 28 table 25. bit description of int_msk1 register bit bit description msk _pg_ldo4 ldo4 power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk _uvlo uvlo interrupt source mask 0: interrupt is enabled 1: interrupt is masked table 26. int_msk2 register name: int_msk2 address: $05 type: rw default: $ff d7 d6 d5 d4 d3 d2 d1 d0 msk_tsd msk_wnrg msk_ildo4 msk_ildo3 msk_ildo2 msk_ildo1 spare = 1 spare = 1 table 27. bit description of int_msk2 register bit bit description msk _ildo1 ldo1 over current interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk _ildo2 ldo2 over current interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk _ildo3 ldo3 over current interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk _ildo4 ldo4 over current interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk _wnrg thermal warning interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk _tsd thermal shutdown interrupt source mask 0: interrupt is enabled 1: interrupt is masked table 28. reset register name: reset address: $10 type: rw default: $10 d7 d6 d5 d4 d3 d2 d1 d0 forcerst spare=0 spare=0 rststatus spare=0 spare=0 rearm
ncP6924 http://onsemi.com 29 table 29. bit description of reset register bit bit description rearm[1:0] rearming of device after tsd 00: re ? arming active after tsd with reset of i 2 c registers: new power ? up sequence is initiated with de- fault i 2 c registers values (default) 01: re ? arming active after tsd with no reset of i 2 c registers: new power ? up sequence is initiated with i 2 c registers values 10: no re ? arming after tsd 11: n/a rststatus reset indicator bit 0: must be written to 0 after register reset 1: default (loaded after registers reset) forcerst force reset bit 0: default 1: force reset of internal registers to default table 30. pid (product identification) register name: pid address: $11 type: r default: d7 d6 d5 d4 d3 d2 d1 d0 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 table 31. rid: (revision identification) register name: rid address: $12 type: r default: d7 d6 d5 d4 d3 d2 d1 d0 rid7 rid6 rid5 rid4 rid3 rid2 rid1 rid0 table 32. fid (features identification) register name: fid address: $13 type: r default: d7 d6 d5 d4 d3 d2 d1 d0 fid7 fid6 fid5 fid4 fid3 fid2 fid1 fid0 table 33. enable register name: enable address: $14 type: rwm default: $fa d7 d6 d5 d4 d3 d2 d1 d0 enldo4 enldo3 enldo2 enldo1 endcdc2 modedcdc2 endcdc1 modedcdc1 table 34. bit description of enable register bit bit description modedcdc1 dcdc1 operating mode 0: auto switching pfm / pwm 1: forced pwm (default) endcdc1 dcdc1 enabling 0: disabled 1: enabled
ncP6924 http://onsemi.com 30 table 34. bit description of enable register bit bit description modedcdc2 dcdc2 operating mode 0: auto switching pfm / pwm 1: forced pwm (default) endcdc2 dcdc2 enabling 0: disabled 1: enabled enldo1 ldo1 enabling 0: disabled 1: enabled enldo2 ldo2 enabling 0: disabled 1: enabled enldo3 ldo3 enabling 0: disabled 1: enabled enldo4 ldo4 enabling 0: disabled 1: enabled table 35. dis register name: dis address: $15 type: rw default: $3f d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 disldo4 disldo3 disldo2 disldo1 disdcdc2 disdcdc1 table 36. bit description of dis register bit bit description disdcdc1 dcdc1 active output discharge 0: disabled 1: enabled disdcdc2 dcdc2 active output discharge 0: disabled 1: enabled disldo1 ldo1 active output discharge 0: disabled 1: enabled disldo2 ldo2 active output discharge 0: disabled 1: enabled disldo3 ldo3 active output discharge 0: disabled 1: enabled disldo4 ldo4 active output discharge 0: disabled 1: enabled table 37. pgood1 register name: pgood1 address: $16 type: rw default: $43 d7 d6 d5 d4 d3 d2 d1 d0 i2c_disable pgassign_rst pgassign_ldo4 pgassign_ldo3 pgassign_ldo2 pgassign_ldo1 pgassign_dcdc2 pgassign_dcdc1
ncP6924 http://onsemi.com 31 table 38. bit description of pgood1 register bit bit description pgassign_dcdc1 dcdc1 power good assignment 0: not assigned 1: assigned to pg pin pgassign_dcdc2 dcdc2 power good assignment 0: not assigned 1: assigned to pg pin pgassign_ldo1 ldo1 power good assignment 0: not assigned 1: assigned to pg pin pgassign_ldo2 ldo2 power good assignment 0: not assigned 1: assigned to pg pgassign_ldo3 ldo3 power good assignment 0: not assigned 1: assigned to pg pin pgassign_ldo4 ldo4 power good assignment 0: not assigned 1: assigned to pg pin pgassign_rst internal reset signal assignment 0: not assigned 1: assigned to pg pin i2c_disable i 2 c interface enabling 0: enabled 1: disabled table 39. pgood2 register name: pgood2 address: $17 type: rw default: $00 d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 pgassign_dvs2 pgassign_dvs1 spare=0 spare=0 spare=0 spare=0 table 40. bit description of pgood2 register bit bit description pgassign_dvs1 dcdc1 dvs assignment 0: not assigned 1: assigned to pg pin pgassign_dvs2 dcdc2 dvs assignment 0: not assigned 1: assigned to pg pin table 41. time register name: time address: $38 type: rw default: 0$00 d7 d6 d5 d4 d3 d2 d1 d0 go2 go1 spare=0 dvs[1:0] tor[2:0]
ncP6924 http://onsemi.com 32 table 42. bit description of time register bit bit description tor[2:0] power good out of reset delay time (ms) 000: 0(default) 001: 8 010: 16 011: 32 100: 64 101: 128 110: 256 111: 512 dvs[1:0] dvs timing ( s) 00: 1.33 s (default) 01: 2.67 s 10: 5.33 s 11: 10.67 s go1 0: dcdc1 output voltage set to vprogdcdc1[7:0] 1: dcdc1 output voltage set to vdvsdcdc1[7:0] go2 0: dcdc2 output voltage set to vprogdcdc2[7:0] 1: dcdc2 output voltage set to vdvsdcdc2[7:0] table 43. bucktap register name: bucktap address: $19 type: rw default: $08 d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 dcdc2_t[2:0] dcdc1_t[2:0] table 44. ldotap1 register name: ldotap1 address: $1a type: rw default: $1a d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 ldo2_t[2:0] ldo1_t[2:0] table 45. ldotap2 register name: ldotap2 address: $1b type: rw default: $2c d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 ldo4_t[2:0] ldo3_t[2:0] table 46. start ? up delay ldox_t[2:0] / dcdcx_t[2:0] start ? up delay 000 2 ms 001 4 ms 010 6 ms 011 8 ms 100 10 ms 101 12 ms 110 14 ms 111 16 ms
ncP6924 http://onsemi.com 33 table 47. vprogdcdc1[7:0] register name: vprogdcdc1 address: $20 type: rw default: $34 d7 d6 d5 d4 d3 d2 d1 d0 vprogdcdc1[7:0] table 48. vdvsdcdc1[7:0] register name: vdvsdcdc1 address: $21 type: rw default: $34 d7 d6 d5 d4 d3 d2 d1 d0 vdvsdcdc1[7:0] table 49. vprogdcdc2[7:0] register name: vprogdcdc2 address: $22 type: rw default: $64 d7 d6 d5 d4 d3 d2 d1 d0 vprogdcdc2[7:0] table 50. vdvsdcdc2[7:0] register name: vdvsdcdc2 address: $23 type: rw default: $64 d7 d6 d5 d4 d3 d2 d1 d0 vdvsdcdc2[7:0] table 51. vprogdcdcx[7:0] and vdvsdcdcx[7:0] bits description bit[7:0] v out (v) bit [7:0] v out (v) bit [7:0] v out (v) bit [7:0] v out (v) $00 0.6000 $40 1.4000 $80 2.2000 $c0 3.0000 $01 0.6125 $41 1.4125 $81 2.2125 $c1 3.0125 $02 0.6250 $42 1.4250 $82 2.2250 $c2 3.0250 $03 0.6375 $43 1.4375 $83 2.2375 $c3 3.0375 $04 0.6500 $44 1.4500 $84 2.2500 $c4 3.0500 $05 0.6625 $45 1.4625 $85 2.2625 $c5 3.0625 $06 0.6750 $46 1.4750 $86 2.2750 $c6 3.0750 $07 0.6875 $47 1.4875 $87 2.2875 $c7 3.0875 $08 0.7000 $48 1.5000 $88 2.3000 $c8 3.1000 $09 0.7125 $49 1.5125 $89 2.3125 $c9 3.1125 $0a 0.7250 $4a 1.5250 $8a 2.3250 $ca 3.1250 $0b 0.7375 $4b 1.5375 $8b 2.3375 $cb 3.1375 $0c 0.7500 $4c 1.5500 $8c 2.3500 $cc 3.1500 $0d 0.7625 $4d 1.5625 $8d 2.3625 $cd 3.1625 $0e 0.7750 $4e 1.5750 $8e 2.3750 $ce 3.1750 $0f 0.7875 $4f 1.5875 $8f 2.3875 $cf 3.1875 $10 0.8000 $50 1.6000 $90 2.4000 $d0 3.2000 $11 0.8125 $51 1.6125 $91 2.4125 $d1 3.2125
ncP6924 http://onsemi.com 34 table 51. vprogdcdcx[7:0] and vdvsdcdcx[7:0] bits description bit[7:0] v out (v) bit [7:0] v out (v) bit [7:0] v out (v) bit [7:0] v out (v) $12 0.8250 $52 1.6250 $92 2.4250 $d2 3.2250 $13 0.8375 $53 1.6375 $93 2.4375 $d3 3.2375 $14 0.8500 $54 1.6500 $94 2.4500 $d4 3.2500 $15 0.8625 $55 1.6625 $95 2.4625 $d5 3.2625 $16 0.8750 $56 1.6750 $96 2.4750 $d6 3.2750 $17 0.8875 $57 1.6875 $97 2.4875 $d7 3.2875 $18 0.9000 $58 1.7000 $98 2.5000 $d8 3.3000 $19 0.9125 $59 1.7125 $99 2.5125 $d9 3.3000 $1a 0.9250 $5a 1.7250 $9a 2.5250 $da 3.3000 $1b 0.9375 $5b 1.7375 $9b 2.5375 $db 3.3000 $1c 0.9500 $5c 1.7500 $9c 2.5500 $dc 3.3000 $1d 0.9625 $5d 2.4525 $9d 2.5625 $dd 3.3000 $1e 0.9750 $5e 1.7750 $9e 2.5750 $de 3.3000 $1f 0.9875 $5f 1.7875 $9f 2.5875 $df 3.3000 $20 1.0000 $60 1.8000 $a0 2.6000 $e0 3.3000 $21 1.0125 $61 1.8125 $a1 2.6125 $e1 3.3000 $22 1.0250 $62 1.8250 $a2 2.6250 $e2 3.3000 $23 1.0375 $63 1.8375 $a3 2.6375 $e3 3.3000 $24 1.0500 $64 1.8500 $a4 2.6500 $e4 3.3000 $25 1.0625 $65 1.8625 $a5 2.6625 $e5 3.3000 $26 1.0750 $66 1.8750 $a6 2.6750 $e6 3.3000 $27 1.0875 $67 1.8875 $a7 2.6875 $e7 3.3000 $28 1.1000 $68 1.9000 $a8 2.7000 $e8 3.3000 $29 1.1125 $69 1.9125 $a9 2.7125 $e9 3.3000 $2a 1.1250 $6a 1.9250 $aa 2.7250 $ea 3.3000 $2b 1.1375 $6b 1.9375 $ab 2.7375 $eb 3.3000 $2c 1.1500 $6c 1.9500 $ac 2.7500 $ec 3.3000 $2d 1.1625 $6d 1.9625 $ad 2.7625 $ed 3.3000 $2e 1.1750 $6e 1.9750 $ae 2.7750 $ee 3.3000 $2f 1.1875 $6f 1.9875 $af 2.7875 $ef 3.3000 $30 1.2000 $70 2.0000 $b0 2.8000 $f0 3.3000 $31 1.2125 $71 2.0125 $b1 2.8125 $f1 3.3000 $32 1.2250 $72 2.0250 $b2 2.8250 $f2 3.3000 $33 1.2375 $73 2.0375 $b3 2.8375 $f3 3.3000 $34 1.2500 $74 2.0500 $b4 2.8500 $f4 3.3000 $35 1.2625 $75 2.0625 $b5 2.8625 $f5 3.3000 $36 1.2750 $76 2.0750 $b6 2.8750 $f6 3.3000 $37 1.2875 $77 2.0875 $b7 2.8875 $f7 3.3000 $38 1.3000 $78 2.1000 $b8 2.9000 $f8 3.3000 $39 1.3125 $79 2.1125 $b9 2.9125 $f9 3.3000 $3a 1.3250 $7a 2.1250 $ba 2.9250 $fa 3.3000 $3b 1.3375 $7b 2.1375 $bb 2.9375 $fb 3.3000
ncP6924 http://onsemi.com 35 table 51. vprogdcdcx[7:0] and vdvsdcdcx[7:0] bits description bit[7:0] v out (v) bit [7:0] v out (v) bit [7:0] v out (v) bit [7:0] v out (v) $3c 1.3500 $7c 2.1500 $bc 2.9500 $fc 3.3000 $3d 1.3625 $7d 2.1625 $bd 2.9625 $fd 3.3000 $3e 1.3750 $7e 2.1750 $be 2.9750 $fe 3.3000 $3f 1.3875 $7f 2.1875 $bf 2.9875 $ff 3.3000 table 52. vprogldo1[5:0] registers name: vprogldo1 address: $24 type: rw default: $24 d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 vprogldo1[5:0] table 53. vprogldo2[5:0] registers name: vprogldo2 address: $25 type: rw default: $10 d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 vprogldo2[5:0] table 54. vprogldo3[5:0] registers name: vprogldo3 address: $26 type: rw default: $24 d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 vprogldo3[5:0] table 55. vprogldo4[5:0] registers name: vprogldo4 address: $27 type: rw default: $10 d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 vprogldo4[5:0] table 56. vprogldox[5:0] bits description vprogldox [5:0] v out (v) vprogldox [5:0] v out (v) vprogldox [5:0] v out (v) vprogldox [5:0] v out (v) 000000 1.00 010000 1.80 100000 2.60 110000 3.30 000001 1.05 010001 1.85 100001 2.65 110001 3.30 000010 1.10 010010 1.90 100010 2.70 110010 3.30 000011 1.15 010011 1.95 100011 2.75 110011 3.30 000100 1.20 010100 2.00 100100 2.80 110100 3.30 000101 1.25 010101 2.05 100101 2.85 110101 3.30 000110 1.30 010110 2.10 100110 2.90 110110 3.30 000111 1.35 010111 2.15 100111 2.95 110111 3.30 001000 1.40 011000 2.20 101000 3.00 111000 3.30 001001 1.45 011001 2.25 101001 3.05 111001 3.30
ncP6924 http://onsemi.com 36 table 56. vprogldox[5:0] bits description vprogldox [5:0] v out (v) vprogldox [5:0] v out (v) vprogldox [5:0] v out (v) vprogldox [5:0] v out (v) 001010 1.50 011010 2.30 101010 3.10 111010 3.30 001011 1.55 011011 2.35 101011 3.15 111011 3.30 001100 1.60 011100 2.40 101100 3.20 111100 3.30 001101 1.65 011101 2.45 101101 3.25 111101 3.30 001110 1.70 011110 2.50 101110 3.30 111110 3.30 001111 1.75 011111 2.55 101111 3.30 111111 3.30 application information power state indicator processor interrupt processor i c battery or system supply processor or system supply dcdc1 out dcdc2 out 4.7 uf 1. 0uf i c ncP6924 interrupt supply monitoring core power up sequencer thermal protection avin agnd sda scl pg hwen intb endcdc1 endcdc2 enldo1 enldo2 enldo3 enldo4 system supply 4. 7uf 10uf 1uh fb11 pvin1 sw1 pgnd1 dcdc1 up to 1.0 a d6 e5 e6 c6 system supply 10uf 1uh fb2 pvin2 sw2 pgnd2 dcdc2 up to 850 ma c5 system or dcdc supply system or dcdc supply ldo1 out ldo2 out 2.2uf 2.2uf ldo4 out 2.2uf ldo3 out 2.2uf system or dcdc supply ldo1 300 ma ldo2 300 ma ldo3 150 ma ldo4 150 ma vin1 vout1 vin2 vout2 vout3 vin34 vout4 a4 a3 e3 e2 c1 b1 a1 enabling c2 d3 d5 d2 d1 a5 b2 a2 e5 d4 b5 e1 b3 figure 39. typical application schematic a6 b4 b6 inductor selection ncP6924 dcdc converters typically use 1 h inductor. use of different values can be considered to optimize operation in specific conditions. the inductor parameters directly related to device performances are saturation current, dc resistance and inductance value. the inductor ripple current ( i l ) decreases with higher inductance. i l v o 1 v o v in l f sw (eq. 1) i lmax i omax i l 2 (eq. 2) with: ? fsw = switching frequency (typical 3 mhz) ? l = inductor value ? i l = peak ? to ? peak inductor ripple current ? i lmax = maximum inductor current to achieve better efficiency, ultra low dc resistance inductor should be selected.
ncP6924 http://onsemi.com 37 the saturation current of the inductor should be higher than the i lmax calculated with the above equations. table 57. inductor l = 1.0 h supplier part # size (mm) (l x l x t) dc rated current (a) dcr max at 25 c (m ) tdk tfm252010a ? 1r0m 2.5 x 2.0 x 1.0 3.5 65 tdk tfm201610a ? 1r0m 2.0 x 1.6 x 1.0 2.5 75 murata lqh44pn ? 1r0np0 4.0 x 3.5 x 1.8 2.5 36 murata lqm2hpn ? 1r0mg0 2.5 x 2.0 x 1.0 1.6 69 toko dfe252012c ? 1r0n 2.5 x 2.0 x 1.2 3.0 59 table 58. inductor l = 2.2 h supplier part # size (mm) (l x l x t) dc rated current (a) dcr max at 25 c (m ) tdk tfm252010a ? 2r2m 2.5 x 2.0 x 1.0 2.3 115 tdk tfm201610a ? 2r2m 2.0 x 1.6 x 1.0 1.7 200 murata lqh44pn ? 2r2mp0 4.0 x 3.5 x 1.8 1.8 59 murata lqm2hpn ? 2r2mg0 2.5 x 2.0 x 1.0 1.3 100 toko dfe252012c ? 2r2n 2.5 x 2.0 x 1.2 2.0 108 output capacitor selection for dc to dc converters selecting the proper output capacitor is based on the desired output ripple voltage. ncP6924 dcdc converters typically use 10uf output capacitor. ceramic capacitors with low esr values will have the lowest output ripple voltage and are strongly recommended. the output capacitor requires either an x7r or x5r dielectric. the output ripple voltage in pwm mode can be estimated by: v o v o 1 v o v in l f sw 1 2 c o f sw esr (eq. 3) table 59. recommended output capacitor for dc to dc converters manufacturer part number case size heighttyp. (mm) c ( f) murata grm188r60j106me47 0603 0.8 10 murata grm219r60j106ke19 0805 1.25 10 murata grm21br60j226me39 0805 1.25 22 tdk c1608x5r0c106k/m 0603 0.8 10 tdk c2012x5r0c106k/m 0805 1.25 10 tdk c2012x5r0c226k/m 0805 1.25 22 input capacitor selection for dc to dc converters in pwm operating mode, the input current is pulsating with large switching noise. using an input bypass capacitor can reduce the peak current transients drawn from the input supply source, thereby reducing switching noise significantly. the maximum rms current occurs at 50% duty cycle with maximum output current, which is of maximum output current. a low profile ceramic capacitor of 4.7 f should be used for most of the cases. for effective bypass results, the input capacitor should be placed as close as possible to pvin1 and pvin2 pins. table 60. recommended input capacitor for dc to dc converters supplier part number casesize heighttyp. (mm) c ( f) murata grm188r60j475ke 0603 0.8 4.7 murata grm188r60j106me 0603 0.8 10 tdk c1608x5r0c475k/m 0603 0.8 4.7 tdk c1608x5r0c106k/m 0603 0.8 10 output capacitor for ldos for stability reason, a typical 2.2uf ceramic output capacitor is suitable for ldos. the ldo output capacitor should be placed as close as possible to the ncP6924 output pin. input capacitor for ldos ncP6924 ldos do not require specific input capacitors. however, a typical 1uf ceramic capacitor placed close to ldos? input is helpful for load transient. power input of ldo can be connected to main power supply. however, for optimum efficiency and lower ncP6924 thermal dissipation, the lowest voltage available in the system is preferred. input voltage of each ldo should always be higher than v out + v ldodrop (v drop , ldo dropout voltage at maximum current). capacitor dc bias characteristics real capacitance of ceramic capacitor changes versus dc voltage. special care should be taken to dc bias effect in order to make sure that the real capacitor value is always higher than the minimum allowable capacitor value specified. pcb layout recommendation the high speed operation of the ncP6924 demands careful attention to board layout and component placement. to prevent electromagnetic interference (emi) problems and reduce voltage ripple of the device , any high current copper trace which see high frequency switching should be optimized. therefore, use short and wide traces for power current paths and for power ground tracks, power plane and ground plane are recommended if possible . both the inductor and input/output capacitor of each dc to dc converters are in the high frequency switching path where current flow may be discontinuous. these components should be placed as close to ncP6924 as
ncP6924 http://onsemi.com 38 possible to reduce parasitic inductance connection. also it is important to minimize the area of the switching nodes and use the ground plane under them to minimize cross ? talk to sensitive signals and ics. it?s suggested to keep as complete of a ground plane under ncP6924 as possible. pgnd and agnd pin connection must be connected to the ground plane. care should be taken to avoid noise interference between pgnd and agnd. it is always good practice to keep the sensitive tracks such as feedback connection (fb1 / fb2) away from switching signal connections (sw1 / sw2) by laying the tracks on the other side or inner layers of pcb. figure 40. recommended pcb layout thermal considerations careful attention must be paid to the power dissipation of the ncP6924. the power dissipation is a function of efficiency and output power. hence, increasing the output power requires better components selection. care should be taken of ldo v drop , the larger it is, the higher dissipation it will bring to ncP6924. keep a large copper plane under and close to ncP6924 is helpful for thermal dissipation .
ncP6924 http://onsemi.com 39 ordering information device marking comment package shipping ? ncP6924afcht1g* 6924ah hwen default version (see detailed description) wlcsp30 (pb?free) 3000 / tape & reel ncP6924afcet1g* 6924ae enabled default version (see detailed description) ncP6924bfcht1g* 6924bh hwen version (see detailed description) ncP6924cfcht1g* 6924ch hwen version (see detailed description) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this is flip chip package without die coating demo board available: the ncP6924gevb/d evaluation board configures the device in typical application to supply constant voltage.
ncP6924 http://onsemi.com 40 package dimensions wlcsp30, 2.46x2.06 case 567cu issue a seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 2.46 bsc e b 0.24 0.29 e 0.40 bsc 0.60 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 30x b 45 c b a 0.10 c a a1 a2 c 0.17 0.23 2.06 bsc 0.25 30x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.10 c 2x top view side view bottom view note 3 e a2 recommended package outline 123 pitch d e pitch a1 0.33 0.39 6 e/2 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncP6924/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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